The Intel 8086 / 8088 / 80186 / 80286 / 80386 / 80486 Instruction Set

This HTML version of the public domain file intel.doc from the PC Game Programmer's guide was produced by me, Zack Smith. HTML modifications are therefore copyrighted © 2005, 2009 by Zack Smith all rights reserved. This information is provided in the hope that it will be useful, but without any warranty. It is provided AS-IS, without even the implied warranty of fitness for a particular purpose.

Intel 8086/80186/80286/80386/80486 Family Architecture
Instruction Clock Cycle Calculation
8088/8086 Effective Address (EA) Calculation
Task State Calculation
FLAGS - Intel 8086 Family Flags Register
MSW - Machine Status Word (286+ only)

The Instructions
AAA - Ascii Adjust for Addition AAD - Ascii Adjust for Division AAM - Ascii Adjust for Multiplication AAS - Ascii Adjust for Subtraction ADC - Add With Carry ADD - Arithmetic Addition AND - Logical And ARPL - Adjusted Requested Privilege Level of Selector (286+ PM) BOUND - Array Index Bound Check (80188+) BSF - Bit Scan Forward (386+) BSR - Bit Scan Reverse (386+) BSWAP - Byte Swap (486+) BT - Bit Test (386+) BTC - Bit Test with Compliment (386+) BTR - Bit Test with Reset (386+) BTS - Bit Test and Set (386+) CALL - Procedure Call CBW - Convert Byte to Word CDQ - Convert Double to Quad (386+) CLC - Clear Carry CLD - Clear Direction Flag CLI - Clear Interrupt Flag (disable) CLTS - Clear Task Switched Flag (286+ privileged) CMC - Complement Carry Flag CMP - Compare CMPS - Compare String (Byte, Word or Doubleword) CMPXCHG - Compare and Exchange CWD - Convert Word to Doubleword CWDE - Convert Word to Extended Doubleword (386+) DAA - Decimal Adjust for Addition DAS - Decimal Adjust for Subtraction DEC - Decrement DIV - Divide ENTER - Make Stack Frame (80188+) ESC - Escape HALT - Halt	F2XM1 - Compute 2x-1 FABS - Absolute value FADD - Floating point add FADDP - Floating point add and pop FBLD - Load BCD FBSTP - Store BCD and pop FCHS - Change sign FCLEX - Clear exceptions FNCLEX - Clear exceptions / no wait FCOM - Floating point compare FCOMP - Floating point compare and pop FCOMPP - Floating point compare and pop twice FCOS - Floating point cosine (387+) FDECSTP - Decrement floating point stack pointer FDISI - Disable interrupts (8087 only; others do fnop) FNDISI - Disable interrupts no wait (8087 only; others do fnop) FDIV - Floating divide FDIVP - Floating divide and pop FDIVR - Floating divide reversed FDIVRP - Floating divide reversed and pop FENI - Enable interrupts (8087 only; others do fnop) FNENI - Enable interrupts nowait (8087 only; others do fnop) FFREE - Free register FIADD - Integer add FICOM - Integer compare FICOMP - Integer compare and pop FIDIV - Integer divide FIDIVR - Integer divide reversed FILD - Load integer FIMUL - Integer multiply FINCSTP - Increment floating point stack pointer FINIT - Initialize floating point processor FNINIT - Initialize floating point processor no wait FIST - Store integer FISTP - Store integer and pop FISUB - Integer subtract FISUBR - Integer subtract reversed FLD - Floating point load FLDZ - Load constant onto stack: 0.0 FLD1 - Load constant onto stack: 1.0 FLDL2E - Load constant onto stack: logarithm base 2 (e) FLDL2T - Load constant onto stack: logarithm base 2 (10) FLDLG2 - Load constant onto stack: logarithm base 10 (2) FLDLN2 - Load constant onto stack: natural logarithm (2) FLDPI - Load constant onto stack: pi (3.14159...) FLDCW - Load control word FLDENV - Load environment state FMUL - Floating point multiply FMULP - Floating point multiply and pop FNOP - no operation FPATAN - Partial arctangent FPREM - Partial remainder FPREM1 - Partial remainder (IEEE compatible, 387+) FPTAN - Partial tangent FRNDINT - Round to integer FRSTOR - Restore saved state FSAVE - Save FPU state FSAVEW - Save FPU state / 16-bit format (387+) FSAVED - Save FPU state / 32-bit format (387+) FNSAVE - Save FPU state no wait FNSAVEW - Save FPU state no wait / 16-bit format (387+) FNSAVED - Save FPU state no wait / 32-bit format (387+) FSCALE - Scale by factor of 2 FSETPM - Set protected mode (287 only; 387+ = fnop) FSIN - Sine (387+) FSINCOS - Sine and cosine (387+) FSQRT - Square root FST - Floating point store FSTP - Floating point store and pop FSTCW - Store control word FNSTCW - Store control word no wait FSTENV - Store FPU environment FSTENVW - Store FPU environment / 16-bit format (387+) FSTENVD - Store FPU environment / 32-bit format (387+) FNSTENV - Store FPU environment no wait FNSTENVW - Store FPU environment no wait / 16-bit format (387+) FNSTENVD - Store FPU environment no wait / 32-bit format (387+) FSTSW - Store status word FNSTSW - Store status word no wait FSUB - Floating point subtract FSUBP - Floating point subtract and pop FSUBR - Floating point reverse subtract FSUBRP - Floating point reverse subtract and pop FTST - Floating point test for zero FUCOM - Unordered floating point compare (387+) FUCOMP - Unordered floating point compare and pop (387+) FUCOMPP - Unordered floating point compare and pop twice (387+) FWAIT - Wait while FPU is executing FXAM - Examine condition flags FXCH - Exchange floating point registers FXTRACT - Extract exponent and significand FYL2X - Compute Y * log2(x) FYL2XP1 - Compute Y * log2(x+1)	HLT - Halt CPU IDIV - Signed Integer Division IMUL - Signed Multiply IN - Input Byte or Word From Port INC - Increment INS - Input String from Port (80188+) INT - Interrupt INTO - Interrupt on Overflow INVD - Invalidate Cache (486+) INVLPG - Invalidate Translation Look-Aside Buffer Entry (486+) IRET/IRETD - Interrupt Return Jxx - Jump Instructions Table JCXZ/JECXZ - Jump if Register (E)CX is Zero JMP - Unconditional Jump LAHF - Load Register AH From Flags LAR - Load Access Rights (286+ protected) LDS - Load Pointer Using DS LEA - Load Effective Address LEAVE - Restore Stack for Procedure Exit (80188+) LES - Load Pointer Using ES LFS - Load Pointer Using FS (386+) LGDT - Load Global Descriptor Table (286+ privileged) LIDT - Load Interrupt Descriptor Table (286+ privileged) LGS - Load Pointer Using GS (386+) LLDT - Load Local Descriptor Table (286+ privileged) LMSW - Load Machine Status Word (286+ privileged) LOCK - Lock Bus LODS - Load String (Byte, Word or Double) LOOP - Decrement CX and Loop if CX Not Zero LOOPE/LOOPZ - Loop While Equal / Loop While Zero LOOPNZ/LOOPNE - Loop While Not Zero / Loop While Not Equal LSL - Load Segment Limit (286+ protected) LSS - Load Pointer Using SS (386+) LTR - Load Task Register (286+ privileged) MOV - Move Byte or Word MOVS - Move String (Byte or Word) MOVSX - Move with Sign Extend (386+) MOVZX - Move with Zero Extend (386+) MUL - Unsigned Multiply NEG - Twos Complement Negation NOP - No Operation (90h) NOT - Ones Compliment Negation (Logical NOT) OR - Inclusive Logical OR OUT - Output Data to Port OUTS - Output String to Port (80188+) POP - Pop Word off Stack POPA/POPAD - Pop All Registers onto Stack (80188+) POPF/POPFD - Pop Flags off Stack PUSH - Push Word onto Stack PUSHA/PUSHAD - Push All Registers onto Stack (80188+) PUSHF/PUSHFD - Push Flags onto Stack	RCL - Rotate Through Carry Left RCR - Rotate Through Carry Right REP - Repeat String Operation REPE/REPZ - Repeat Equal / Repeat Zero REPNE/REPNZ - Repeat Not Equal / Repeat Not Zero RET/RETF - Return From Procedure ROL - Rotate Left ROR - Rotate Right SAHF - Store AH Register into FLAGS SAL/SHL - Shift Arithmetic Left / Shift Logical Left SAR - Shift Arithmetic Right SBB - Subtract with Borrow/Carry SCAS - Scan String (Byte, Word or Doubleword) SETAE/SETNB - Set if Above or Equal / Set if Not Below (386+) SETB/SETNAE - Set if Below / Set if Not Above or Equal (386+) SETBE/SETNA - Set if Below or Equal / Set if Not Above (386+) SETE/SETZ - Set if Equal / Set if Zero (386+) SETNE/SETNZ - Set if Not Equal / Set if Not Zero (386+) SETL/SETNGE - Set if Less / Set if Not Greater or Equal (386+) SETGE/SETNL - Set if Greater or Equal / Set if Not Less (386+) SETLE/SETNG - Set if Less or Equal / Set if Not greater or Equal (386+) SETG/SETNLE - Set if Greater / Set if Not Less or Equal (386+) SETS - Set if Signed (386+) SETNS - Set if Not Signed (386+) SETC - Set if Carry (386+) SETNC - Set if Not Carry (386+) SETO - Set if Overflow (386+) SETNO - Set if Not Overflow (386+) SETP/SETPE - Set if Parity / Set if Parity Even (386+) SETNP/SETPO - Set if No Parity / Set if Parity Odd (386+) SGDT - Store Global Descriptor Table (286+ privileged) SIDT - Store Interrupt Descriptor Table (286+ privileged) SHL - Shift Logical Left SHR - Shift Logical Right SHLD/SHRD - Double Precision Shift (386+) SLDT - Store Local Descriptor Table (286+ privileged) SMSW - Store Machine Status Word (286+ privileged) STC - Set Carry STD - Set Direction Flag STI - Set Interrupt Flag (Enable Interrupts) STOS - Store String (Byte, Word or Doubleword) STR - Store Task Register (286+ privileged) SUB - Subtract TEST - Test For Bit Pattern VERR - Verify Read (286+ protected) VERW - Verify Write (286+ protected) WAIT/FWAIT - Event Wait WBINVD - Write-Back and Invalidate Cache (486+) XCHG - Exchange XLAT/XLATB - Translate XOR - Exclusive OR

Intel 8086 Family Architecture

General Purpose Registers
AH/AL AX (EAX)	Accumulator
BH/BL BX (EBX)	Base
CH/CL CX (ECX)	Counter
DH/DL DX (EDX)	Data

(Exx) indicates 386+ 32 bit register

Segment Registers
CS	Code Segment
SS	Stack Segment
DS	Data Segment
ES	Extra Segment
(FS)	386 and newer
(GS)	386 and newer

Pointer Registers	Stack Registers
SI (ESI) Source Index	SP (ESP) Stack Pointer
DI (EDI) Destination Index	BP (EBP) Base Pointer
IP Instruction Pointer

Status Registers
FLAGS	Status Flags

Special Registers (386+ only)
CR0	Control Register 0	DR0	Debug Register 0
CR2	Control Register 2	DR1	Debug Register 1
CR3	Control Register 3	DR2	Debug Register 2
		DR3	Debug Register 3
TR4	Test Register 4	DR6	Debug Register 6
TR5	Test Register 5	DR7	Debug Register 7
TR6	Test Register 6
TR7	Test Register 7

Register	Default Segment	Valid Overrides
BP	SS	DS, ES, CS
SI or DI	DS	ES, SS, CS
DI strings	ES	None
SI strings	DS	ES, SS, CS

Instruction Clock Cycle Calculation

Some instructions require additional clock cycles due to a "Next Instruction Component" identified by a "+m" in the instruction clock cycle listings. This is due to the prefetch queue being purge on a control transfers. Below is the general rule for calculating "m":

88/86: Not applicable
286: "m" is the number of bytes in the next instruction
386: "m" is the number of components in the next instruction (the instruction coding (each byte); plus the data and the displacement are all considered components)

8088/8086 Effective Address (EA) Calculation

Description	Clock Cycles
Displacement	6
Base or Index (BX,BP,SI,DI)	5
Displacement+(Base or Index)	9
Base+Index (BP+DI,BX+SI)	7
Base+Index (BP+SI,BX+DI)	8
Base+Index+Displacement (BP+DI,BX+SI)	11
Base+Index+Displacement (BP+SI+disp,BX+DI+disp)	12

add 4 cycles for word operands at odd addresses
add 2 cycles for segment override
80188/80186 timings differ from those of the 8088/8086/80286

Task State Calculation

"TS" is defined as switching from VM/486 or 80286 TSS to one of the following:

	New Task
Old Task	486 TSS (VM=0)	486 TSS (VM=1)	386 TSS (VM=0)	386 TSS (VM=1)	286 TSS
386 TSS (VM=0)			309	226	282
386 TSS (VM=1)			314	231	287
386 CPU/286 TSS			307	224	280
486 CPU/286 TSS	199	177			180

Miscellaneous

All timings are for best case and do not take into account wait states, instruction alignment, the state of the prefetch queue, DMA refresh cycles, cache hits/misses or exception processing.
To convert clocks to nanoseconds divide one microsecond by the processor speed in MegaHertz: (1000MHz/(n MHz)) = X nanoseconds

FLAGS - Intel 8086 Family Flags Register

Bit # (in hex)	Acronym	Description
0	CF	Carry flag
1		1
2	PF	Parity
3		0
4	AF	Auxiliary flag
5		0
6	ZF	Zero flag
7	SF	Sign flag
8	TP	Trap flag (single step)
9	IF	Interrupt flag
A	DF	Direction flag
B	OF	Overflow flag
C/D	IOPL	IOPL I/O Privilege Level (286+ only)
E	NT	Nested Task Flag (286+ only)
F	0
10	RF	Resume Flag (386+ only)
11	VM	Virtual Mode Flag (386+ only)
12	AC	Alignment Check (486SX+ only)
13	VIF	Virtual Interrupt Flag (Pentium+)
14	VIP	Virtual Interrupt Pending (Pentium+)
15	ID	Indentification (Pentium+)

MSW - Machine Status Word (286+ only)

Bit #	Acronym	Description
0	PE	Protection Enable, switches processor between protected and real mode
1	MP	Math Present, controls function of the WAIT instruction
2	EM	Emulation, indicates whether coprocessor functions are to be emulated
3	TS	Task Switched, set and interrogated by coprocessor on task switches and when interpretting coprocessor instructions
4	ET	Extension Type, indicates type of coprocessor in system
5-30	Reserved
31	PG	Paging, indicates whether the processor uses page tables to translate linear addresses to physical addresses